-- Quartus II VHDL Template
-- Single port RAM with single read/write address 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Achtung_const.all;

entity SRAM_driver is
	port 
	(
		clk		: in std_logic;
		rst		: in std_logic;
		
		SRAM_D	: inout SRAM_Data;
		SRAM_A	: out SRAM_Address;
		SRAM_WE	: out std_logic;
		SRAM_CE	: out std_logic;
		SRAM_OE	: out std_logic;
		SRAM_UB	: out std_logic;
		SRAM_LB	: out std_logic;
	
	
		row 		:in unsigned(9 downto 0);
		column 		:in unsigned(9 downto 0);
	
		pixel_in 	: in std_logic_vector(1 downto 0);
		pixel_out 	: out std_logic_vector(1 downto 0);
	
	
		command		: in std_logic_vector(1 downto 0);
		done		: out std_logic
	);

end entity;

architecture rtl of SRAM_driver is

	type state is (RAM_IDLE, RAM_WRITE, RAM_READ);
	signal next_state, current_state: state;
	signal adr : std_logic_vector(19 downto 0);

begin

process(column)
begin
	if((column(0)) = '1') then
		SRAM_LB <= '0';
		SRAM_UB <= '1';
	else
		SRAM_LB <= '1';
		SRAM_UB <= '0';
	end if;
end process;

process (clk, rst, command, row, column, adr, SRAM_D, pixel_in)
begin

	if(rst = '0') then
		SRAM_CE <= '1';
		SRAM_WE <= '1';
		SRAM_OE <= '1';
		SRAM_D <= "ZZZZZZZZZZZZZZZZ";
		SRAM_A <= (others => '0');
		adr <= "00000000000000000000";
		pixel_out <= "00";
		done <= '0';
	next_state <= RAM_IDLE;
	else 
	
		adr <= std_logic_vector((row * 320) + (column srl 1));
		SRAM_A <= adr(17 downto 0);
		
		
			
			if(command = "01") then	
					SRAM_CE <= '0';
					SRAM_OE <= '0';
					SRAM_WE <= '1';
					if((column(0)) = '1') then
						pixel_out <= SRAM_D(1 downto 0);
					else
						pixel_out <= SRAM_D(9 downto 8);
					end if;
					done <='1';
					SRAM_D <= (others => 'Z');
			elsif(command = "10") then 
					SRAM_CE <= '0';
					SRAM_WE <= '0';
					SRAM_OE <= '1';
					if((column(0)) = '1') then
						SRAM_D <= "00000000000000" & pixel_in;
					else
						SRAM_D <= "000000" & pixel_in & "00000000";
					end if;
					done <='1';
			else
					SRAM_CE <= '1';
					SRAM_WE <= '1';
					SRAM_OE <= '1';
					SRAM_D <= (others => 'Z');
					done <= '0';
			end if;
		
		
	end if;

end process;


end rtl;





